CIPHER performs research in microelectronic applications, tools, architectures, and materials to enhance the security, trust, and reliability of microelectronic devices, hardware platforms, and the critical systems which rely upon them. CIPHER researchers develop tools and techniques in the areas of assurance, anti-tamper, and reliability for FPGAs, ASICs, System on a Chip, microcontrollers, and other devices, leveraging custom and formal methods. They further develop assured operations in enterprise, embedded, and cyber-physical systems via novel hardware-oriented security and trust protections and offer cutting-edge research and development in all aspects of configurable computing, such as analysis, emulation, and application of FPGAs using conventional and custom software EDA/CAD tools.
Hardware Security and Trust Publications
| Abi-Karam, Stefan, Rishov Sarkar, Suhail Basalama, Jason Cong, and Callie Hao FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs 31st Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, China, Jan. 2026 | |
| Travis Haroldsen, Osaze Shears, Dallon Glick, Jay Danner Using Open-Source EDA for BIST to Address FPGA Assurance GOMACTech 2026 | |
| Christopher Clark, Theodore Franklin, T. Robert Harris, Paul Jo, Peter McMenamin, Michael Pekala, Billbang Sayasean, Benjamin B. Yang, Michael Grasta, Rajanish Pandey, Dylan Robertson, Petteri Litmanen, Mauricio Pinto, Spencer Pace, Byron Bullis, Wen Shu, Ted Jones, Paul Mosinskis, Steven Goldner, Brett Attaway, Dana Sturzebecher, Darin Heckendorn Mixed Signal Product Development Using State-of-the Art Tools in a Collaborative Design Environment GOMACTech 2026 | |
| Stefan Abi-Karam, Cong Hao HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks IEEE International Conference on LLM-Aided Design (LAD), Stanford, California, June 2025 | |
| Jacob Alward, Christian Bottenfield, John Brooks, Meredith Caveney, Jacob Campbell, Christopher Clark, Christopher Coen, Theodore Franklin, T. Robert Harris, Stephen Hurst, Paul Jo, Robert Lingle Jr., Brandon Lovelace, Nelson Lourenco, Peter McMenamin, Robert Moreland, Taylor Peterson, Leif Sandstrom, Billbang Sayasean, Maxwell Tannenbaum, Tucker Turner, J. Glen Vinson, Laura Vinson, Anthony Zenere, Andrew Stark, Benjamin B. Yang Packaging and Subsystem Integration of a Monolithic Radio Frequency, Photonic, and Digital Integrated Circuit for High-Speed Radio Frequency Processing GOMACTech 2025 | |
| Frank Werner, Christopher Clark Effects of Injected Signal Properties on Power Spectrum Analysis for Recycled FPGA Detection GOMACTech 2025 | |
| Mark Lee, Chris Clark, Saibal Mukhopadhyay A Compute-in-Memory Ascon Implementation Based on a Novel 11T SRAM Processing Macro IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), April 2025 | |
| Chris Clark Non-Invasive Reliability and Authenticity Assessment of Microelectronic Devices Hardware, Electronics & Advanced Technologies Symposium (HEAT), July 2025 | |
| Hannah Mahon, Shane Kosieradzki Encrypted Matrix Multiplication Using 3-Dimensional Rotations OpenFHE, October 2025 | |
| Hannah Mahon Digital Circuit Formal Verification Macaulay2 Workshop at Tulane University, April 2025. | |
| Frank Werner Approaches for Detecting Recycled FPGA Devices 2025 Microelectronics Reliability and Qualification Workshop (MRQW), February 2025. | |
| Benjamin B. Yang, Christopher Coen, Nelson Lourenco GTRI Integrated Circuit Research Cadence Connect Industry Meeting (Invited Presentation), April 2025. | |
| Rishov Sarkar, Rachel Paul, and Cong Hao LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization 32nd IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM) | |
| Abi-Karam, Stefan, Rishov Sarkar, Allison Seigler, Sean Lowe, Zhigang Wei, Hanqiu Chen, Nanditha Rao, Lizy John, Aman Arora, and Cong Hao HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 6th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), Utah, Sept. 2024 (Best Paper Award) | |
| Frank T. Werner, Stephen Hurst, and Christopher R. Clark Comparison of Approaches for Detecting Recycled FPGA Devices GOMACTech 2024 | |
| Travis Haroldsen, Dallon Glick, and Jay Danner Built-in Self-Test for Intel FPGAs GOMACTech 2024 | |
| A. Stark, J. Alward, C. Bottenfield, J. Campbell, M. Caveney, C. Clark, C. Coen, T. Franklin, S. Hurst, P. Jo, R. Lingle, N. Lourenco, B. Lovelace, P. McMenamin, T. Peterson, L. Sandstrom, B. Sayasean, M. Tannenbaum, T. Turner, B.B. Yang, A. Zenere, D. Kozak, E. Kamp, J. Hawke Co-Design of Monolithic RF and Photonic Integrated Circuits with Packaging GOMACTech 2024 | |
| Chris Clark Independent FPGA Assurance and Verification Research Air Force Safety Center (AFSEC) Independent Verification Organization (IVO) Summit, Dec. 2024 | |
| M. Lee, C. Clark and S. Mukhopadhyay A Pre-Silicon Physical Design Study Towards Mitigating EMSCA on Cryptographic ICs IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024 | |
| Bill Hunter, and Lee Lerner Emerging Side-Channel Threats and Protection for FPGAs Hardware, Electronics & Advanced Technologies Symposium (HEAT), July 2024. | |
 | C. R. Clark, W. Stuckey, N. Braswell, T. Haroldsen, T.-Y. Sung, and O. Shears |
 | Efficient Porting of FPGA Independent Testing Within and Across Vendors |
 | Photonic Integrated Circuits: Assessment of State-of-the-Art Manufacturing Industrial Base Capabilities and Needs (PICASSO’S MUSICIANS) |
 | Monolithic Integration of RF and Digital Electronics with Photonics for a High-Bandwidth Coherent Driver Modulator |
 | FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference |
 | Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters |
 | Independent Functional Test for Microsemi FPGAs |
 | Multicolor Ramsey numbers for Berge cycles |
 | A S/C/X/Ku-band, 4-Tap, Digitally Controllable Analog FIR Filter with Reconfigurable Bandwidth and RF Filtering Profile |
| Classifying Computations on Multi-Tenant FPGAs |
 | A Tunable Dual-Edge Time-to-Digital Converter |
| Independent Testing of Untrusted FPGAs for Faulty Interconnect |
 | Canary: An FPGA Assurance Plugin for Vendor EDA Tools |
 | Memory-Loss Resilient Controller Design for Temporal Logic Constraints |
 | Mapping Electromagnetic Fields in Active Electronic Devices via Novel Scanning Probe Techniques |
 | Establishing Trust in Microelectronics |
 | Improved Techniques for Sensing Intra-Device Side Channel Leakage |
 | Are novel scanning-probe field sensors a tamper threat? |
 | Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems |
 | Rapid Precedent-Aware Pedestrian and Car Classification on Constrained IoT Platforms |
 | Multi-Modal Web-Based Dashboards for Geo-Located Real-Time Monitoring |
 | The Trustworthy Autonomic Interface Guardian Architecture for Cyber-Physical Systems |
 | Isolating Trust in an Industrial Control System-on-Chip Architecture |
People
Laboratory Director, Cybersecurity, Information Protection, and Hardware Evaluation Research Laboratory
